Western Digital Delivers New Innovations to Drive Open Standard Interfaces and RISC-V Processor Development

/ -- Company Announces Plans to Open Source New RISC-V SweRV Core to Accelerate Development of Purpose-Built Architectures from Core to Edge
(Photo: https://mma.prnewswire.com/media/796625/SweRV_Core.jpg )
"As Big Data and Fast Data continues to proliferate, purpose-built technologies are essential for unlocking the true value of data across today's wide-ranging data-centric applications," said Fink. "Our SweRV Core and the new cache coherency fabric initiative demonstrate the significant possibilities that can be realized by bringing data closer to processing power. These planned contributions to the open-source community and continued commitment of the RISC-V initiative offer exciting potential to accelerate collaborative innovation and data-driven discoveries."

"Speeds, feeds, and brute compute is no longer the winning formula for edge and endpoint computing. As more data moves to the edge for real-time processing and inferencing, configurable architectures will be better suited to meet the needs of heavy and often dynamic application workloads, especially for those driven by artificial intelligence and Internet of Things," said Mario Morales, program vice president, enabling technologies and semiconductors, IDC. "Power efficiency, configurability, and low power will become the key metrics for edge and endpoint computing architectures."
Availability and Resources
Western Digital's SweRV ISS and OmniXtend architecture are available now for download at the following locations:

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