'Increasing design complexity creates need for verification tools'

As designs get more and more complex in the fast evolving electronic design industry, verification and testing of design is getting even more tedious, expensive and time consuming. This is increasing the need for electronic design automation (EDA) tools for design verification.

Design complexity is increasing because of the trend to miniaturise design and integrate multi-functional units into a single chip. Thus design verification is consuming an ever-increasing portion of IC development time and cost and as much as 80 per cent of effort in a complex IC design project is now devoted to verification.

According to Collett International Research (CIR) which gives quantitative data on trends in electronic design, almost 50 per cent of the total engineering time is spent on design verification.

"The verification problem is bigger than it has ever been. Its constant increase is based on Moore's law," says Swaminathan Venkat, group director, Verification Group, Synopsys Incorporation.

So to improve verification productivity and also to enhance the quality of complex system-on-chip (SoC), Synopsys today announced the introduction a new "systemverilog testbench" automation tool called Pioneer-NTB. Synopsys is a leading player in the EDA space for semiconductor design.

Verilog is a hardware description language used by electronic designers to describe and design their chip and system prior to fabrication.

This is used for designing Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Array (FPGA), a programmable logic device.

Pioneer-NTB gives customers the opportunity to take advantage of Synopsys' verification technologies. With it "verification teams can deploy the latest methodologies in a mixed-language environment to find more bugs faster with increased productivity," said Swaminathan.