How AL and ML are completely overhauling the complex chip designing process

San Jose-headquartered and Nasdaq listed Cadence Design Systems is going about doing this with the recent launch of Cerebrus, an ML-based tool that automates and scales chip design

Chip design is a complex, design-intensive and time-consuming process. With chip complexity growing and with chips having hundreds of blocks sometimes, the time spent by designers and designer requirements have grown over the years.

San Jose-headquartered and Nasdaq listed Cadence Design Systems wants to change this with the recent launch of Cerebrus, a ML-based tool that automates and scales chip design.

“We have reinforced an ML engine that can improve the productivity of the design by 10x and we can bring in PPA (power, performance, area) improvement by 20 per cent. It provides an automated process from synthesis to sign-off, and is based on distributed computer systems which means we can use cloud machines to run this solutions,” said Venkat Thanvantri, VP of research and development, AL/ML for Digital and Sign off, Cadence.

A chip is divided into blocks, each of which is an independent module and, depending on the complexity each chip, can have hundreds of blocks. Determining the chip design, or in other words floor planning—where each block will fit—is one of the most complex and time consuming exercises of the chip design process. This also requires an army of designers. Each block can take up to 4-5 designers and engineers.

“The semiconductor industry is going through a huge shift driven by 5G, autonomous driving, hyperscale compute and industrial IoT. Next-generation chips must be faster and smarter. Scale becomes an issue as you grow, and that is an area that Cerebrus takes care of scale with few engineers,” explains Thanvantri.

“Previously, design teams didn’t have an automated way to reuse historical design knowledge, leading to excess time spent on manual re-learning with each new project and lost margins,” says Dr Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “The delivery of Cerebrus marks an EDA industry revolution with ML-driven digital chip design where engineering teams have a greater opportunity to provide higher impact in their organisations because they can offload manual processes. As the industry continues to move to advanced nodes and design size and complexity increase, Cerebrus lets designers achieve PPA goals much more efficiently.”

Cadence started to focus on a ML-based tool for chip design 2–3 years back when a team focused on this was created within the company, a team from India too contributed to this. Over the last six to eight months the company has also deployed Cerebrus for some of its customers.

“As Samsung Foundry continues to deploy up-to-date process nodes, we are always looking for innovative ways to exceed PPA in chip implementation. As part of our long-term partnership with Cadence, Samsung Foundry has used Cerebrus and the Cadence digital implementation flow on multiple applications. We’ve observed more than an 8 per cent power reduction on some of our most critical blocks in just a few days versus many months of manual effort. In addition, we are using Cerebrus for automated floorplan power distribution network sizing, which has resulted in more than 50 per cent better final design timing,” said Sangyun Kim, vice president, Design Technology, Samsung Foundry.

Industry efforts

Use of ML and AI in chip designing has been happening for over a decade now. Google has been using ML to help design its next-generation of ML chips. According to a paper in the journal Nature, Google said that it has been able to use deep reinforcement learning approach to chip floor-planning and in under six hours, they have managed to automatically generate floor plans that were superior or comparable to those produced by humans.

In the paper, Google mentions that this development will have major consequences for the chip industry, as it can now allow companies to quickly create architecture space for upcoming designs. Google is already using this in some what it showcased in the research paper commercial.

Nvidia has also been using AI in chip design. In 2020 the company announced Ampere architecture using AI.