Scaling to stacking, chipmakers look beyond Moore's Law to boost computing

From chiplets to vertical stacking, new design approaches are emerging as traditional transistor scaling runs into physical and economic limits

You have likely heard that upcoming phones and laptops will move to 3nm or even 2nm chips. The assumption is straightforward: smaller transistors mean better performance and efficiency. For years, that has largely been true.

 

But that approach is now running into limits. As transistors shrink to just a few nanometres, problems such as heat, leakage, and manufacturing complexity begin to outweigh the gains. The cost of each new generation rises sharply, while improvements become harder to sustain.

 

This is forcing the semiconductor industry to rethink a basic question: if chips cannot keep getting smaller in the same way, how else can computing power be increased?

 

Why shrinking worked for so long

At the core of every chip are transistors, which act as tiny switches controlling the flow of electricity. Packing more transistors into a chip allows it to perform more operations at once, while smaller transistors also reduce the distance signals need to travel, improving speed and efficiency.

This is what made Moore’s Law possible. Each generation delivered more performance in roughly the same space, enabling steady progress in everything from smartphones to cloud computing.

 

However, as transistor sizes approach atomic scales, controlling their behaviour becomes more difficult. Electrical leakage increases, heat becomes harder to dissipate, and the precision required for manufacturing rises significantly.

 

At that point, simply shrinking transistors is no longer enough.

Different approaches to scaling beyond Moore’s Law

As traditional scaling slows, companies are exploring multiple directions rather than a single replacement.

 

One approach is to make chips significantly larger. Wafer-scale engines (WSE), used by companies like Cerebras, take an entire silicon wafer and turn it into a single processor. This avoids the need to connect multiple chips together, reducing data movement and latency. It is particularly suited for AI training, where massive amounts of data need to move quickly between compute units.

 

However, these systems are expensive, difficult to manufacture, and highly specialised. They are not designed for general-purpose computing or consumer devices.

 

Another approach is vertical stacking at the wafer level. TSMC’s wafer-on-wafer, or WoW, technology bonds entire wafers together, enabling dense vertical interconnects between layers. This improves bandwidth and reduces latency by shortening the distance data needs to travel, making it useful for compact, high-performance systems such as smartphones and laptops.

 

The drawback is manufacturing complexity. Because entire wafers are bonded, defects in one layer can affect the corresponding layer above. This makes yield management critical and limits flexibility.

 

A more modular version of stacking is used in Intel’s Foveros technology. Instead of bonding whole wafers, it stacks smaller dies or “chiplets” using vertical interconnects, often on top of a base die. This allows different components to be built on different process nodes and combined into a single package.

 

This improves flexibility and manufacturing efficiency, but it still relies on interconnects between separate dies. As a result, it cannot eliminate data movement bottlenecks in the same way as a fully integrated design.

The limitation of current 3D stacking

Across these approaches, a common constraint remains. Most existing 3D designs are built by stacking pre-fabricated layers. That means the connections between layers are added after manufacturing, which limits how tightly components can be integrated. Even in advanced designs, these vertical links are far less dense than the connections within a single layer of silicon.

 

This is where the next step in chip design is being explored.

A different kind of 3D chip

Researchers at the University of Illinois Urbana-Champaign have published a paper, which focuses on monolithic 3D integration, which takes a different approach to stacking.

 

Instead of bonding separate layers, circuits are built directly on top of each other, layer by layer. This allows much finer alignment between layers and significantly denser vertical connections, bringing them closer to the density seen within a single plane.

 

Until now, the main barrier has been temperature. Conventional silicon fabrication requires heat levels (up to 1000 degree celsius) that would damage previously built layers, making true multi-layer construction impractical.

The researchers address this by using ultra-thin silicon sheets, around 10 nanometres thick, which can be transferred and processed at temperatures below 200 degree celsius.

 

They also use junctionless transistors, which avoid high-temperature fabrication steps. This allows multiple layers of silicon circuits to be built without degrading earlier ones, while maintaining performance comparable to standard silicon devices.

 

In their demonstration, the team stacked three layers of circuits and achieved yields close to 100 per cent, indicating that the process can be reliable at small scales.

Where this could fit

Compared to existing approaches, monolithic 3D integration attempts to solve the main limitation of stacking: the quality of connections between layers.

 

If successful at scale, it could offer the density benefits of vertical stacking without the performance penalties associated with large interconnects. That makes it particularly relevant for workloads where data movement is a bottleneck, including AI and high-performance computing.