Tieups key to facing growing complexity in chip design

The semiconductor value chain is evolving as a result of pressures on both demand and supply side. With convergence defining the market and the consumer electronic market growing, global investment trends show it is not enough to build technically cutting-edge chips.

It is even more important to make chips the market needs and reach them to the market in time.

Addressing the 'Thought Leadership Forum' by Indian Semiconductor Association, Michael J Fister, CEO and president, Cadence Design System, said that no single group is investing in all the categories of chip design and collaboration is the key. The challenges for semiconductor design is complexity of design as well as complexity in designing.

Design is getting more complex with design works expanding to the smallest level of chip "" ROW. ROW is a part of RAM (random access memory) array and a bit data is stored where a column and a row intersect.

The complexity of design implies greater time is required for verification of design and complexity in designing means increase in time to market. "To manage these are the challenges, we face," said Michael J Fister.

He added that there is a need for a holistic solution for this and a greater interaction between system concept and physical design to accelerate the integration into the system.